DP Aux 的二三事 - 其二 - DPCD

日期：
DisplayPort 2.0 - DPCD Field Address Mapping

DPCD

DisplayPort的 DPCD（DisplayPort Configuration Data）
可以理解成「DisplayPort 裝置之間用來交換能力與設定資訊的暫存器空間」。
提供 DP Link Training、Lane 數、Link Rate、Sink 能力、MST、HDR/Adaptive-Sync 等功能的核心。

硬體上使用DP的 pin 15 AUX_CH(p), pin 17 AUX_CH(n) 或 Type-C SBU1/SBU2

簡化流程

讀 Sink Capability ↓ 設定 Link Rate / Lane Count ↓ TPS1：Clock Recovery ↓ 讀 Link Status / Adjust Request ↓ TPS2/3/4：Channel EQ ↓ 再次讀 Link Status ↓ Training Success ↓ Disable Training Pattern ↓ Normal Video

1. AUX Read：讀取 Sink Capability

從 DPCD 00000h 開始讀取 Capability， 確認 Sink 支援的最高 Link Rate、Lane 數以及 TPS3 / TPS4 等 Link Training 能力。


詳細

00000h：DPCD_REV。DPCD版本

10h = DPCD r1.0.
11h = DPCD r1.1.
12h = DPCD r1.2.
13h = DPCD r1.3 (for eDP v1.4 DPRX only).
14h = DPCD r1.4.

00001h：MAX_LINK_RATE。傳輸速率

06h = 1.62Gbps/lane (RBR)
0Ah = 2.7Gbps/lane (HBR)
14h = 5.4Gbps/lane (HBR2)
1Eh = 8.1Gbps/lane (HBR3)

00002h：MAX_LANE_COUNT。lane數量

01h = One lane (Lane 0 only).
02h = Two lanes (Lanes 0 and 1 only).
04h = Four lanes (Lanes 0, 1, 2, and 3).

2. AUX Write：設定 Link Configuration

Source 寫入 Link Configuration Registers 00100h設定頻寬及lane數量


詳細

00100h：LINK_BW_SET。頻寬設定

06h = 1.62Gbps/lane (RBR).
0Ah = 2.7Gbps/lane (HBR).
14h = 5.4Gbps/lane (HBR2).
1Eh = 8.1Gbps/lane (HBR3).

00101h：LANE_COUNT_SET。lane數量設定

01h = One lane (Lane 0 only).
02h = Two lanes (Lanes 0 and 1 only).
04h = Four lanes (Lanes 0, 1, 2, and 3).

3. TPS1：Clock Recovery

Source 送出 Training Pattern 1 (TPS1)， 進行 Clock Recovery。

Source 讀取： DPCD 00202h ~ 00207h 來確認每條 Lane 的 CR 狀態。

如果 Clock Recovery 尚未成功，Source 會依照 Sink 的Adjust Request 調整：

  • Voltage Swing
  • Pre-emphasis

詳細

TRAINING

00102h：TRAINING_PATTERN_SET。訓練模型設定，設定值依DPCD版本而有不同

DPCD r1.4 8b/10b_TRAINING_PATTERN_SELECT
0h = Training not in progress (or disabled; default).
1h = Link Training Pattern Sequence 1 (TPS1).
2h = Link Training Pattern Sequence 2 (TPS2).
3h = Link Training Pattern Sequence 3 (TPS3).
7h = Link Training Pattern Sequence 4 (TPS4).

00103h：TRAINING_LANE0_SET。開始 lane 0 訓練

  • [1:0] VOLTAGE_SWING_SET
    • 00b = Voltage Swing Level 0.
01b = Voltage Swing Level 1.
10b = Voltage Swing Level 2.
11b = Voltage Swing Level 3.
  • [4:3] PRE-EMPHASIS_SET
    • 00b = Pre-emphasis Level 0.
01b = Pre-emphasis Level 1.
10b = Pre-emphasis Level 2.
11b = Pre-emphasis Level 3.

00104h：TRAINING_LANE1_SET。開始 lane 1 訓練

00105h：TRAINING_LANE2_SET。開始 lane 2 訓練

00106h：TRAINING_LANE3_SET。開始 lane 3 訓練

CHECK

00202h：LANE0_1_STATUS。Lane 0 and Lane 1狀態，CR_DONE數值 1 為成功

  • [0]：LANE0_CR_DONE
  • [1]：LANE0_CHANNEL_EQ_DONE
  • [2]：LANE0_SYMBOL_LOCKED
  • [4]：LANE1_CR_DONE
  • [5]：LANE1_CHANNEL_EQ_DONE
  • [6]：LANE1_SYMBOL_LOCKED

00203h：LANE2_3_STATUS。Lane 2 and Lane 3狀態，CR_DONE數值 1 為成功

  • [0]：LANE2_CR_DONE
  • [1]：LANE2_CHANNEL_EQ_DONE
  • [2]：LANE2_SYMBOL_LOCKED
  • [4]：LANE3_CR_DONE
  • [5]：LANE3_CHANNEL_EQ_DONE
  • [6]：LANE3_SYMBOL_LOCKED

00204h：LANE_ALIGN_STATUS_UPDATED。

  • [7]：LINK_STATUS_UPDATED。數值 1，Link Status和Adjust Request有更新，讀取後為0

ADJUST

若CR_DONE為0 (失敗)，則讀取SINK的Adjust Request調整，然後再重新training

00206h：ADJUST_REQUEST_LANE0_1。

  • [1:0] VOLTAGE_SWING_LANE0
    • 00b = Level 0.
01b = Level 1.
10b = Level 2.
11b = Level 3.
  • [3:2] PRE_EMPHASIS_LANE0 (內容同上)
  • [5:4] VOLTAGE_SWING_LANE1 (內容同上)
  • [7:6] PRE_EMPHASIS_LANE1 (內容同上)

00207h：ADJUST_REQUEST_LANE2_3。

  • [1:0] VOLTAGE_SWING_LANE2
    • 00b = Level 0.
01b = Level 1.
10b = Level 2.
11b = Level 3.
  • [3:2] PRE_EMPHASIS_LANE2 (內容同上)
  • [5:4] VOLTAGE_SWING_LANE3 (內容同上)
  • [7:6] PRE_EMPHASIS_LANE3 (內容同上)

RE-TRAINING

依Adjust Request讀取的值，再回到00103h ~ 00106h重新training

4. TPS2 / TPS3 / TPS4：Channel Equalization

Clock Recovery 成功後，進入 Channel Equalization 階段。

Source 依 Sink Capability 選擇 TPS2、TPS3 或 TPS4， 並再次讀取： DPCD 00202h ~ 00207h

確認：

  • Clock Recovery Done
  • Channel Equalization Done
  • Symbol Lock
  • Inter-Lane Alignment

詳細

TRAINING

00102h：TRAINING_PATTERN_SET。訓練模型設定，設定值依DPCD版本而有不同

DPCD r1.4 8b/10b_TRAINING_PATTERN_SELECT
0h = Training not in progress (or disabled; default).
1h = Link Training Pattern Sequence 1 (TPS1).
2h = Link Training Pattern Sequence 2 (TPS2).
3h = Link Training Pattern Sequence 3 (TPS3).
7h = Link Training Pattern Sequence 4 (TPS4).

00103h：TRAINING_LANE0_SET。開始 lane 0 訓練

  • [1:0] VOLTAGE_SWING_SET
    • 00b = Voltage Swing Level 0.
01b = Voltage Swing Level 1.
10b = Voltage Swing Level 2.
11b = Voltage Swing Level 3.
  • [4:3] PRE-EMPHASIS_SET
    • 00b = Pre-emphasis Level 0.
01b = Pre-emphasis Level 1.
10b = Pre-emphasis Level 2.
11b = Pre-emphasis Level 3.

00104h：TRAINING_LANE1_SET。開始 lane 1 訓練

00105h：TRAINING_LANE2_SET。開始 lane 2 訓練

00106h：TRAINING_LANE3_SET。開始 lane 3 訓練

CHECK

00202h：LANE0_1_STATUS。Lane 0 and Lane 1狀態，EQ_DONE / SYMBOL_LOCKED數值 1 為成功

  • [0]：LANE0_CR_DONE
  • [1]：LANE0_CHANNEL_EQ_DONE
  • [2]：LANE0_SYMBOL_LOCKED
  • [4]：LANE1_CR_DONE
  • [5]：LANE1_CHANNEL_EQ_DONE
  • [6]：LANE1_SYMBOL_LOCKED

00203h：LANE2_3_STATUS。Lane 2 and Lane 3狀態，EQ_DONE / SYMBOL_LOCKED 1 為成功

  • [0]：LANE2_CR_DONE
  • [1]：LANE2_CHANNEL_EQ_DONE
  • [2]：LANE2_SYMBOL_LOCKED
  • [4]：LANE3_CR_DONE
  • [5]：LANE3_CHANNEL_EQ_DONE
  • [6]：LANE3_SYMBOL_LOCKED

00204h：LANE_ALIGN_STATUS_UPDATED。

  • [7]：LINK_STATUS_UPDATED。數值 1，Link Status和Adjust Request有更新，讀取後為0

ADJUST

EQ_DONE / SYMBOL_LOCKED為0 (失敗)，則讀取SINK的Adjust Request調整，然後再重新training

00206h：ADJUST_REQUEST_LANE0_1。

  • [1:0] VOLTAGE_SWING_LANE0
    • 00b = Level 0.
01b = Level 1.
10b = Level 2.
11b = Level 3.
  • [3:2] PRE_EMPHASIS_LANE0 (內容同上)
  • [5:4] VOLTAGE_SWING_LANE1 (內容同上)
  • [7:6] PRE_EMPHASIS_LANE1 (內容同上)

00207h：ADJUST_REQUEST_LANE2_3。

  • [1:0] VOLTAGE_SWING_LANE2
    • 00b = Level 0.
01b = Level 1.
10b = Level 2.
11b = Level 3.
  • [3:2] PRE_EMPHASIS_LANE2 (內容同上)
  • [5:4] VOLTAGE_SWING_LANE3 (內容同上)
  • [7:6] PRE_EMPHASIS_LANE3 (內容同上)

RE-TRAINING

依Adjust Request讀取的值，再回到00103h ~ 00106h重新training

5. Disable Training Pattern

當所有 Link Training 條件成功後：

CR Done → EQ Done → Symbol Lock → Inter-Lane Alignment

Source 停止 Training Pattern，開始傳送正常的 Main Stream / Video。


詳細

00102h：TRAINING_PATTERN_SET。停止training把值設為 0

DPCD r1.4 8b/10b_TRAINING_PATTERN_SELECT
0h = Training not in progress (or disabled; default).
1h = Link Training Pattern Sequence 1 (TPS1).
2h = Link Training Pattern Sequence 2 (TPS2).
3h = Link Training Pattern Sequence 3 (TPS3).
7h = Link Training Pattern Sequence 4 (TPS4).

DPCD： DisplayPort Configuration Data。DPCD 是透過 AUX Channel 存取的 byte-addressed configuration space。

1. DPCD Field Address Mapping

Table 2-182 — DPCD Field Address Mapping
DPCD Address DPCD Field 詳細定義
00000h – 000FFh Receiver Capability Table 2-183
00100h – 001FFh Link Configuration Table 2-184
00200h – 002FFh Link/Sink Device Status Table 2-185
00300h – 003FFh Source Device-specific Table 2-186
00400h – 004FFh Sink Device-specific Table 2-187
00500h – 005FFh Branch Device-specific Table 2-188
00600h – 006FFh Link/Sink Device Power Control Table 2-189
00700h – 007FFh eDP-specific Table 2-190
01000h – 017FFh Sideband MSG Buffers Table 2-191
02000h – 021FFh DPRX Event Status Indicator Table 2-192
02200h – 022FFh Extended Receiver Capability Table 2-193
03000h – 030FFh Protocol Converter Extension Table 2-194
60000h – 61CFFh Multi-touch (for eDP) Table 2-195
68000h – 69FFFh HDCP 1.3 and HDCP 2.2 Table 2-196
F0000h – F02FFh LT-tunable PHY Repeater Table 2-197
FFF00h – FFFFFh MyDP-specific Table 2-198

2. 常用 DPCD Register

Address Register 用途
00000h DPCD_REV DPCD Revision
00001h MAX_LINK_RATE Sink 支援的最大 Link Rate
00002h MAX_LANE_COUNT Sink 支援的最大 Lane 數
00003h MAX_DOWNSPREAD Down-spread / No AUX handshake capability
00100h LINK_BW_SET 目前設定的 Link Rate
00101h LANE_COUNT_SET 目前啟用的 Lane 數
00102h TRAINING_PATTERN_SET Link Training Pattern
00200h SINK_COUNT 目前 Sink / Branch device 數量
00202h LANE0_1_STATUS Lane 0 / Lane 1 Link Status
00203h LANE2_3_STATUS Lane 2 / Lane 3 Link Status
00204h LANE_ALIGN_STATUS_UPDATED Lane Alignment / Status Updated
00205h SINK_STATUS Sink Status

3. Link Training 常用區域

Address Register 功能
00100h LINK_BW_SET 設定 Link Rate
00101h LANE_COUNT_SET 設定 Lane Count
00102h TRAINING_PATTERN_SET 設定 Training Pattern
00103h TRAINING_LANE0_SET 設定 Lane 0 Voltage Swing / Pre-emphasis
00104h TRAINING_LANE1_SET 設定 Lane 1 Voltage Swing / Pre-emphasis
00105h TRAINING_LANE2_SET 設定 Lane 2 Voltage Swing / Pre-emphasis
00106h TRAINING_LANE3_SET 設定 Lane 3 Voltage Swing / Pre-emphasis
00202h LANE0_1_STATUS 讀取 Lane 0 / 1 CR、EQ、Symbol Lock
00203h LANE2_3_STATUS 讀取 Lane 2 / 3 CR、EQ、Symbol Lock
00204h LANE_ALIGN_STATUS_UPDATED 確認 Lane Alignment
00206h ADJUST_REQUEST_LANE0_1 Sink 要求調整 Lane 0 / 1
00207h ADJUST_REQUEST_LANE2_3 Sink 要求調整 Lane 2 / 3
Note：
DisplayPort 2.0 同時支援傳統 8b/10b 以及 128b/132b channel coding。 除非規範特別指出，DPCD registers 原則上適用於兩種 channel coding。

Reference: VESA DisplayPort Standard, Version 2.0, Section 2.12.3 — DPCD Field Address Mapping, Table 2-182.

Capability

DPCD除了00000h：標準的 Sink capability 16 bytes之外，
還有02200h：Extended Receiver Capability，內容和相同

DP v1.3或更新的版本則使用 Extended Receiver Capability

00008h~0000Bh 是 Receive Port capability，
0000Ch~0000Fh 則是後續的 I²C/eDP/training/adapter capability
Offset Base Address Extended Address Register
00h 00000h 02200h DPCD_REV
01h 00001h 02201h 8b/10b_MAX_LINK_RATE
02h 00002h 02202h MAX_LANE_COUNT
03h 00003h 02203h MAX_DOWNSPREAD
04h 00004h 02204h NORP_PWR_VOLTAGE_CAP
05h 00005h 02205h DOWN_STREAM_PORT_PRESENT
06h 00006h 02206h MAIN_LINK_CHANNEL_CODING_CAP
07h 00007h 02207h DOWN_STREAM_PORT_COUNT
08h 00008h 02208h RECEIVE_PORT0_CAP_0
09h 00009h 02209h RECEIVE_PORT0_CAP_1
0Ah 0000Ah 0220Ah RECEIVE_PORT1_CAP_0
0Bh 0000Bh 0220Bh RECEIVE_PORT1_CAP_1
0Ch 0000Ch 0220Ch I2C_SPEED_CONTROL_CAP
0Dh 0000Dh 0220Dh EDP_CONFIGURATION_CAP
0Eh 0000Eh 0220Eh 8b/10b_TRAINING_AUX_RD_INTERVAL
0Fh 0000Fh 0220Fh ADAPTER_CAP


LTTPR

Link Training Tunable PHY Repeater 可配置物理層中繼器
它是 DisplayPort 鏈路中的一種信號重定時/中繼器（Repeater），
主要用於改善高速 DP 信號在較長距離、轉接或復雜鏈路中的傳輸質量。
使用DPCD的 F0000h ~ F02FFh

LTTPR DPCD Address Map

LTTPR DPCD Address Range: F0000h ~ F02FFh  |  Total: 0x300 bytes (768 bytes)
Address Range Block Description
F0000h ~ F000Fh LTTPR Capability and ID LT-tunable PHY Repeater DPCD Capability and ID Field。由链路中的 LTTPR 共用。
F0010h ~ F005Fh PHY_Repeater1 PHY Repeater 1 Configuration and Status
F0060h ~ F00AFh PHY_Repeater2 PHY Repeater 2 Configuration and Status
F00B0h ~ F00FFh PHY_Repeater3 PHY Repeater 3 Configuration and Status
F0100h ~ F014Fh PHY_Repeater4 PHY Repeater 4 Configuration and Status
F0150h ~ F019Fh PHY_Repeater5 PHY Repeater 5 Configuration and Status
F01A0h ~ F01EFh PHY_Repeater6 PHY Repeater 6 Configuration and Status
F01F0h ~ F023Fh PHY_Repeater7 PHY Repeater 7 Configuration and Status
F0240h ~ F028Fh PHY_Repeater8 PHY Repeater 8 Configuration and Status
F0290h ~ F02FFh FEC LTTPR FEC LTTPR registers

LTTPR Capability / ID

F0000h ~ F000Fh：LTTPR 共用能力及識別信息


詳細

F0000h：LTTPR Revision

F0001h：Max Link Rate

06h = 1.62Gbps/lane (RBR).
0Ah = 2.7Gbps/lane (HBR).
14h = 5.4Gbps/lane (HBR2).
1Eh = 8.1Gbps/lane (HBR3).

F0002h：Repeater Count，LTTPR 数量

80h = One LTTPR is present.
40h = Two LTTPRs are present.
20h = Three LTTPRs are present.
10h = Four LTTPRs are present.
08h = Five LTTPRs are present.
04h = Six LTTPRs are present.
02h = Seven LTTPRs are present.
01h = Eight LTTPRs are present.
FFh = Nine or more LTTPRs

F0003h：LTTPR Mode

55h = Transparent mode (default).
AAh = Non-transparent mode.

F0004h：Max Lane Count

01h = One lane (Lane 0 only).
02h = Two lanes (Lanes 0 and 1 only).
04h = Four lanes (Lanes 0, 1, 2, and 3).

F0005h：Extended Wake Timeout

PHY Repeater 1

F0010h ~ F005Fh： LTTPR1 的 PHY configuration/status

repeater也需要training，步驟Main Link一樣


詳細

TRAINING

F0010h：TRAINING_PATTERN_SET_PHY_REPEATER1，參數同00102h

F0011h：TRAINING_LANE0_SET_PHY_REPEATER1

  • [1:0] VOLTAGE_SWING_SET
    • 00b = Voltage Swing Level 0.
01b = Voltage Swing Level 1.
10b = Voltage Swing Level 2.
11b = Voltage Swing Level 3.
  • [4:3] PRE-EMPHASIS_SET
    • 00b = Pre-emphasis Level 0.
01b = Pre-emphasis Level 1.
10b = Pre-emphasis Level 2.
11b = Pre-emphasis Level 3.

F0012h：TRAINING_LANE0_SET_PHY_REPEATER2，參數同上

F0013h：TRAINING_LANE0_SET_PHY_REPEATER3，參數同上

F0014h：TRAINING_LANE0_SET_PHY_REPEATER4，參數同上

CHECK

F0030h：LANE0_1_STATUS_PHY_REPEATER1，參數同00202h

F0031h：LANE2_3_STATUS_PHY_REPEATER1，參數同00203h

F0032h：LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1，參數同00204h

ADJUST

F0033h：ADJUST_REQUEST_LANE0_1_PHY_REPEATER1，參數同00206h

F0034h：ADJUST_REQUEST_LANE2_3_PHY_REPEATER1，參數同00207h

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