DP Aux 的二三事 - 其一

日期：

DP AUX（DisplayPort Auxiliary Channel）的功能是作為 DisplayPort 接口中的輔助通信通道，

負責控制、管理和雙向通信。


核心功能可以概括為以下幾類：

一、顯示器識別與配置
  • 讀取顯示器能力（EDID）
    • 支持的分辨率、刷新率
    • 色深、色彩格式
    • HDR、FreeSync / G-Sync 能力等
  • 鏈路配置（Link Training）

    • 用於協商並設置：

    • Lane 數量（1/2/4 lanes）
    • 鏈路速率（RBR / HBR / HBR2 / HBR3 / UHBR）
    • 電壓擺幅(Voltage Swing)與預加重參數(Pre-emphasis)
二、DPCD 訪問（DisplayPort Configuration Data）

AUX 通道用於 讀寫顯示器的 DPCD 寄存器，實現：

  • 顯示器狀態監控
  • 功能開啟/關閉
  • 錯誤狀態反饋
三、I²C-over-AUX（替代傳統 DDC）

AUX 通道用於 讀寫顯示器的 DPCD 寄存器，實現：

  • DP 使用 AUX 通道模擬 I²C 總線：
    • 讀取 EDID（替代 HDMI/VGA 的 DDC）
    • 支持顯示器的 I²C 設備訪問
  • 減少引腳數量，提高抗幹擾能力

Physical Layer

AUX（Auxiliary Channel） 是一條低速、差分、雙向、半雙工的通信通道

DisplayPort AUX 電氣參數（典型值）
參數 典型值 說明
信號類型 差分信號 AUX_P / AUX_N
工作方式 半雙工、雙向 同一對線收發切换
差分擺幅 (Vdiff) ≈ 400 mVpp 典型差分峰峰值
共模电壓 (Vcm) ≈ 0.5 V 接收端偏置
數據速率 ≈ 1 Mbps 低速控制通道
編碼方式 manchester-ii
差分阻抗 100 Ω 走線與終端匹配
耦合方式 AC 耦合 串聯隔直電容
拓樸结構 點對點 非多點總線

Manchester Encoding 曼徹斯特編碼

AUX使用的是Manchester-ii即IEEE 802.3 Ethernet(10BASE-T)版本

  • 位元 0：高 -> 低, falling edge
  • 位元 1：低 -> 高, rising edge

以數值0x14為例，實際波形如下 (差分訊號經比較器輸出為邏輯訊號)


2.11 AUX Transaction Syntax 交易語法

    協議內容分二類：
  • Native AUX transaction syntax : 原生 AUX 交易語法
  • I2C-over-AUX transaction I²C : 交易映射至 AUX

Aux的通訊都是由 主機 發起 Request，裝置 回覆 Reply，無論Write/Read

主機送出Request後會等待400us的timeout，裝置則是有300us的時間來回覆

Aux transaction syntax

所有交易都必須以一個 前導碼（Preamble）「SYNC」 開始，
用於讓 請求端（Requester，DPTX）與回應端（Replier，DPRX）完成同步，並以 「STOP」 條件結束。

Table 2-170: Bit/Byte Size of Various Data Types of AUX Transaction Syntax

Request Transaction for Read

Preamble Command Data
SYNC STOP
(Sync End)		 Command
(4 bits)		 Address
(20 bits)		 Length
(1 byte)		 STOP
  • AUX Requester（DPTX）要從 AUX Replier（DPRX）讀取的位元組數。N 為 1 到 16 的整數。

Request Transaction for Write

Preamble Command Data
SYNC STOP
(Sync End)		 Command
(4 bits)		 Address
(20 bits)		 Length : N
(1 byte)		 Data
(N bytes)		 STOP
  • AUX Requester（DPTX）要寫入 AUX Replier（DPRX）的位元組數。N 為 1 到 16 的整數。

Reply Transaction for Read

Preamble Command Data
SYNC STOP
(Sync End)		 Command
(4 bits)		 0000
(4 bits)		 Length
(N byte)		 STOP
  • 回覆 N 個資料位元組（Data bytes）N 為 1 到 16 的整數，表示已準備好可傳送的資料位元組數。

Reply Transaction for Write

Preamble Command Data
SYNC STOP
(Sync End)		 Command
(4 bits)		 0000
(4 bits)		 0 or 1 byte STOP
  • 當AUX Replier對寫入請求交易（write request transaction）回覆 NACK 時，它應指出已有多少個位元組（bytes）已成功寫入。

2.11.1 Command Definition

2.11.1.1 Request Command Definition

bit 7 6 5 4 3 2 1 0
I2C-over-AUX Transaction
0 1 MOT (Middle-of-Transaction) bit
0 0 Write
0 1 Read
1 0 Write_Status_Update_Request
1 1 RESERVED
DisplayPort Transaction (Native AUX)
1 0 0 0 Write
0 0 1 Read

MOT (Middle-of-Transaction) bit : This bit shall be set when the I2C transaction does not end (or STOP)


2.11.1.2 Reply Command Definition

bit 7 6 5 4 3 2 1 0
I2C-over-AUX Reply field
0 0 I2C ACK
0 1 I2C NACK
1 0 I2C DEFER
1 1 RESERVED
Native AUX Reply field
0 0 AUX_ACK
0 1 AUX_NACK
1 0 AUX_DEFER
1 1 RESERVED



這是一個native write實際的波形

Requester對位置0x107寫入1個byte 0x80，Repiler回覆了ACK確認動作無誤

可以看到在data 0x80後接上STOP，然後Requester釋放了Aux bus的控制(Hi-Z)


native read波形

Requester預對位置0x0000讀取16個bytes，Repiler確認ACK並回覆16 bytes的data


什麼是DP Link Training

DP Link Training 是 Source（顯卡）與 Sink（顯示器）在開始傳送影像前，用來協商並校準實體傳輸鏈路的流程，

確保高速差分訊號能可靠傳輸。

目標是確認：

  • 可用的 Lane 數
  • 可用的 Link Rate
  • 合適的 電壓擺幅（Voltage Swing）
  • 合適的 預加重（Pre-emphasis）

Aux Link Training 的角色

利用 AUX Channel 進行 Link Training 的控制、回饋與狀態交換

AUX Channel 負責：

  • Source 寫入訓練參數
  • Sink 回報訓練結果（Clock Recovery 是否成功等）
  • 讀寫 DPCD Register（0x100~0x11F 等）

Link Training 主要流程（DP 1.x 為例）

  • 能力探索（Capability Discovery）

    • Source 透過 AUX 讀取 Sink 的 DPCD：

    • 最大 Link Rate
    • 最大 Lane Count
    • 是否支援 SSC、TPS3 / TPS4（DP 1.2+）

  • Clock Recovery（CR）Training

    • 目的：讓 Sink 能正確鎖定時鐘。

    流程：

    1.Source 設定初始：

    • Link Rate
    • Lane Count
    • Voltage Swing = Level 0
    • Pre-emphasis = Level 0

    2.Source 傳送 Training Pattern 1 (TPS1)

    3.Sink 透過 DPCD 回報：

    • CLOCK_RECOVERY_DONE（每個 Lane）

    4.若失敗：

    • Source 提高 Voltage Swing / Pre-emphasis
    • 重試（有最大次數限制）

    ✅成功條件：所有 Lane 的 CR 都完成

  • Channel Equalization（EQ）Training

    • 目的：確保資料眼圖品質足夠。

    流程：

    1.Source 傳送 TPS2 / TPS3（依 DP 版本）

    Sink 回報：

    • CHANNEL_EQ_DONE
    • SYMBOL_LOCKED

    3.Source 可能再微調：

    • Voltage Swing
    • Pre-emphasis

    ✅成功條件：CR + EQ 全部完成

  • Link Training Complete

    • Source 停止 Training Pattern
    • 切換到 Normal Video Stream
    • 開始送影像資料（Main Link）

Link Training範例

這是對一塊eDP panel的training過程，Addr對應了DPCD位址

( DPCD 請參考spec的 2.12.3 DPCD Field Address Mapping )


➕Native Write(8) Addr:0x00600 Length:1 Data:01

00600h SET_POWER & SET_DP_PWR_VOLTAGE

[2:0]SET_POWER_STATE: 1,Set local Sink device and all downstream Sink devices to D0 (normal operation mode)

➕Native Read(9) Addr:0x00600 Length:1 Data:01

00600h SET_POWER & SET_DP_PWR_VOLTAGE

[2:0]SET_POWER_STATE: 1,Set local Sink device and all downstream Sink devices to D0 (normal operation mode)

➕Native Read(9) Addr:0x00000 Length:16 Data:14 14 C4 81 00 00 01 C0 02 00 00 00 00 01 01 00

00000h DPCD_REV
    [7:0]Revision Number: 14h, DPCD r1.4
00001h MAX_LINK_RATE
    [7:0]MAX_LINK_RATE: 14h, 5.4Gbps/lane
00002h MAX_LANE_COUNT
    [4:0]MAX_LANE_COUNT: 04h, 4 lanes
    [5]POST_LT_ADJ_REQ_SUPPORTED: 0, Post-Link Training Adjust Request is not supported
    [6]TPS3_SUPPORTED: 1,TPS3 is supported
    [7]ENHANCED_FRAME_CAP: 1,Enhanced Framing symbol sequence for BS and BR is supported
00003h MAX_DOWNSPREAD
    [0]MAX_DOWNSPREAD: 1,Up to 0.5% down-spread
    [6]NO_AUX_TRANSACTION_LINK_TRAINING: 0,Requires AUX transactions to synchronize to a DPTX
    [7]TPS4_SUPPORTED: 1,TPS4 is supported
00004h NORP & DP_PWR_VOLTAGE_CAP
    [0]NORP: 0,One receiver port
    [5]5V_DP_PWR_CAP: 0,Downstream device is not capable of producing +4.9 to +5.5V on the DP_PWR pin of its DP connector
    [6]12V_DP_PWR_CAP: 0,Downstream device is not capable of producing +12V +-10%
    [7]18V_DP_PWR_CAP: 0,Downstream device is not capable of producing +18V +-10%
00005h DOWN_STREAM_PORT_PRESENT
    [0]DFP_PRESENT: 0
    [2:1]DFP_TYPE: 0,DisplayPort
    [3]FORMAT_CONVERSION: 0,This Branch device does not have a format conversion block
    [4]DETAILED_CAP_INFO_AVAILABLE: 0,DFP capability field is 1 byte per port
00006h MAIN_LINK_CHANNEL_CODING
    [0]8b/10b: 1,DisplayPort receiver supports the Main-Link channel coding specification
00007h DOWN_STREAM_PORT_COUNT
    [3:0]DFP_COUNT: 0
    [6]MSA_TIMING_PAR_IGNORED: 1,Sink device is capable of rendering the incoming video stream
    [7]OUI Support: 1,OUI is supported
00008h RECEIVE_PORT0_CAP_0
    [1]LOCAL_EDID_PRESENT: 1,This receiver port has a local EDID
    [2]ASSOCIATED_TO_PRECEDING_PORT: 0,This port is used for the main isochronous stream
    [3]HBLANK_EXPANSION_CAPABLE: 0,DPRX is not capable of Horizontal Blanking Expansion operation
    [4]BUFFER_SIZE_UNIT: 0,Units are in pixel counts
    [5]BUFFER_SIZE_PER_PORT: 0,Buffer size is per-lane
    [6]HBLANK_REDUCTION_CAPABLE: 0,DPRX cannot reduce the HBlank pixel count
00009h RECEIVE_PORT0_CAP_1
    [7:0]BUFFER_SIZE: 32 (0)
0000Ah RECEIVE_PORT1_CAP_0
    [1]LOCAL_EDID_PRESENT: 0,This receiver port does not have a local EDID
    [2]ASSOCIATED_TO_PRECEDING_PORT: 0,This port is used for the main isochronous stream
    [3]HBLANK_EXPANSION_CAPABLE: 0,DPRX is not capable of Horizontal Blanking Expansion operation
    [4]BUFFER_SIZE_UNIT: 0,Units are in pixel counts
    [5]BUFFER_SIZE_PER_PORT: 0,Buffer size is per-lane
    [6]HBLANK_REDUCTION_CAPABLE: 0,DPRX cannot reduce the HBlank pixel count
0000Bh RECEIVE_PORT1_CAP_1
    [7:0]BUFFER_SIZE: 32 (0)
0000Ch I2C Speed Control Capabilities Bit Map
    [7:0]I2C Speed Control Capabilities Bit Map: 00h,RESERVED
0000Dh eDP_CONFIGURATION_CAP
    [0]ALTERNATE_SCRAMBLER_RESET_CAPABLE: 1,Can use the eDP alternate scrambler reset value of FFFEh
    [3]DPCD_DISPLAY_CONTROL_CAPABLE: 0
0000Eh TRAINING_AUX_RD_INTERVAL
    [6:0]TRAINING_AUX_RD_INTERVAL: 01h,100us for the Main-Link Clock Recovery phase; 4ms for the Main-Link Channel Equalization phase
    [7]EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT: 0,Not present
0000Fh ADAPTOR_CAP
    [0]FORCE_LOAD_SENSE_CAP: 0,Does not support VGA force load adaptor sense mechanism
    [1]ALTERNATE_I2C_PATTERN_CAP: 0,Does not support alternate I2C patterns

➕Native Write(8) Addr:0x00100 Length:1 Data:14

00100h LINK_BW_SET

[7:0]MAX_LINK_RATE: 14h,5.4Gbps/lane

➕Native Write(8) Addr:0x00101 Length:1 Data:84

00101h LANE_COUNT_SET

[4:0]LANE_COUNT_SET: 04h,4 lanes

[5]POST_LT_ADJ_REQ_GRANTED: 0

[7]ENHANCED_FRAME_EN: 1,Enhanced Framing symbol sequence for BS and BR is enabled

➕Native Write(8) Addr:0x00007 Length:1 Data:C0

00007h DOWN_STREAM_PORT_COUNT

[3:0]DFP_COUNT: 0

[6]MSA_TIMING_PAR_IGNORED: 1,Sink device is capable of rendering the incoming video stream

[7]OUI Support: 1,OUI is supported

➕Native Read(9) Addr:0x00107 Length:1 Data:00

00107h DOWNSPREAD_CTRL

[4]SPREAD_AMP: 0,Main-Link signal is not down-spread

➕Native Write(8) Addr:0x00107 Length:1 Data:80

00107h DOWNSPREAD_CTRL

[4]SPREAD_AMP: 0,Main-Link signal is not down-spread

上面是確認及設定DP的基本訊息，接下來才是Link Training的過程

➕Native Write(8) Addr:0x00102 Length:5 Data:21 00 00 00 00

00102h TRAINING_PATTERN_SET
    [3:0]TRAINING_PATTERN_SELECT: 1,Link Training Pattern Sequence 1
    [4]RECOVERED_CLOCK_OUT_EN: 0,Recovered clock output from a test pad of DPRX is not enabled
    [5]SCRAMBLING_DISABLE: 1,DPTX disables scrambler and transmits all symbols without scrambling
    [7:6]SYMBOL_ERROR_COUNT_SEL: 0,Count Disparity and Illegal Symbol errors
00103h TRAINING_LANE0_SET
    [1:0]VOLTAGE SWING SET: 0,Voltage swing level 0
    [2]MAX_SWING_REACHED: 0
    [4:3]PRE-EMPHASIS_SET: 0,Pre-emphasis level 0
    [5]MAX_PRE-EMPHASIS_REACHED: 0
00104h TRAINING_LANE1_SET
    [1:0]VOLTAGE SWING SET: 0,Voltage swing level 0
    [2]MAX_SWING_REACHED: 0
    [4:3]PRE-EMPHASIS_SET: 0,Pre-emphasis level 0
    [5]MAX_PRE-EMPHASIS_REACHED: 0
00105h TRAINING_LANE2_SET
    [1:0]VOLTAGE SWING SET: 0,Voltage swing level 0
    [2]MAX_SWING_REACHED: 0
    [4:3]PRE-EMPHASIS_SET: 0,Pre-emphasis level 0
    [5]MAX_PRE-EMPHASIS_REACHED: 0
00106h TRAINING_LANE3_SET
    [1:0]VOLTAGE SWING SET: 0,Voltage swing level 0
    [2]MAX_SWING_REACHED: 0
    [4:3]PRE-EMPHASIS_SET: 0,Pre-emphasis level 0
    [5]MAX_PRE-EMPHASIS_REACHED: 0

➕Native Read(9) Addr:0x00202 Length:6 Data:11 11 80 04 22 22

00202h LANE0_1_STATUS
    [0]LANE0_CR_DONE: 1
    [1]LANE0_CHANNEL_EQ_DONE: 0
    [2]LANE0_SYMBOL_LOCKED: 0
    [4]LANE1_CR_DONE: 1
    [5]LANE1_CHANNEL_EQ_DONE: 0
    [6]LANE1_SYMBOL_LOCKED: 0
00203h LANE2_3_STATUS
    [0]LANE2_CR_DONE: 1
    [1]LANE2_CHANNEL_EQ_DONE: 0
    [2]LANE2_SYMBOL_LOCKED: 0
    [4]LANE3_CR_DONE: 1
    [5]LANE3_CHANNEL_EQ_DONE: 0
    [6]LANE3_SYMBOL_LOCKED: 0
00204h LANE_ALIGN_STATUS_UPDATED
    [0]INTERLANE_ALIGN_DONE: 0
    [1]POST_LT_ADJ_REQ_IN_PROGRESS: 0
    [6]DOWNSTREAM_PORT_STATUS_CHANGED: 0
    [7]LINK_STATUS_UPDATED: 1
00205h SINK_STATUS
    [0]RECEIVE_PORT_0_STATUS: 0,Sink device is out of synchronization
    [1]RECEIVE_PORT_1_STATUS: 0,Sink device is out of synchronization
    [2]STREAM_REGENERATION_STATUS: 1,Stream is being regenerated
00206h ADJUST_REQUEST_LANE0_1
    [1:0]VOLTAGE_SWING_LANE0: 2,Level 2
    [3:2]PRE-EMPHASIS_LANE0: 0,Level 0
    [5:4]VOLTAGE_SWING_LANE1: 2,Level 2
    [7:6]PRE-EMPHASIS_LANE1: 0,Level 0
00207h ADJUST_REQUEST_LANE2_3
    [1:0]VOLTAGE_SWING_LANE0: 2,Level 2
    [3:2]PRE-EMPHASIS_LANE0: 0,Level 0
    [5:4]VOLTAGE_SWING_LANE1: 2,Level 2
    [7:6]PRE-EMPHASIS_LANE1: 0,Level 0

➕Native Write(8) Addr:0x00102 Length:5 Data:23 00 00 00 00

00102h TRAINING_PATTERN_SET
    [3:0]TRAINING_PATTERN_SELECT: 3,Link Training Pattern Sequence 3
    [4]RECOVERED_CLOCK_OUT_EN: 0,Recovered clock output from a test pad of DPRX is not enabled
    [5]SCRAMBLING_DISABLE: 1,DPTX disables scrambler and transmits all symbols without scrambling
    [7:6]SYMBOL_ERROR_COUNT_SEL: 0,Count Disparity and Illegal Symbol errors
00103h TRAINING_LANE0_SET
    [1:0]VOLTAGE SWING SET: 0,Voltage swing level 0
    [2]MAX_SWING_REACHED: 0
    [4:3]PRE-EMPHASIS_SET: 0,Pre-emphasis level 0
    [5]MAX_PRE-EMPHASIS_REACHED: 0
00104h TRAINING_LANE1_SET
    [1:0]VOLTAGE SWING SET: 0,Voltage swing level 0
    [2]MAX_SWING_REACHED: 0
    [4:3]PRE-EMPHASIS_SET: 0,Pre-emphasis level 0
    [5]MAX_PRE-EMPHASIS_REACHED: 0
00105h TRAINING_LANE2_SET
    [1:0]VOLTAGE SWING SET: 0,Voltage swing level 0
    [2]MAX_SWING_REACHED: 0
    [4:3]PRE-EMPHASIS_SET: 0,Pre-emphasis level 0
    [5]MAX_PRE-EMPHASIS_REACHED: 0
00106h TRAINING_LANE3_SET
    [1:0]VOLTAGE SWING SET: 0,Voltage swing level 0
    [2]MAX_SWING_REACHED: 0
    [4:3]PRE-EMPHASIS_SET: 0,Pre-emphasis level 0
    [5]MAX_PRE-EMPHASIS_REACHED: 0

➕Native Read(9) Addr:0x00202 Length:6 Data:77 77 81 04 44 44

00202h LANE0_1_STATUS
    [0]LANE0_CR_DONE: 1
    [1]LANE0_CHANNEL_EQ_DONE: 1
    [2]LANE0_SYMBOL_LOCKED: 1
    [4]LANE1_CR_DONE: 1
    [5]LANE1_CHANNEL_EQ_DONE: 1
    [6]LANE1_SYMBOL_LOCKED: 1
00203h LANE2_3_STATUS
    [0]LANE2_CR_DONE: 1
    [1]LANE2_CHANNEL_EQ_DONE: 1
    [2]LANE2_SYMBOL_LOCKED: 1
    [4]LANE3_CR_DONE: 1
    [5]LANE3_CHANNEL_EQ_DONE: 1
    [6]LANE3_SYMBOL_LOCKED: 1
00204h LANE_ALIGN_STATUS_UPDATED
    [0]INTERLANE_ALIGN_DONE: 1
    [1]POST_LT_ADJ_REQ_IN_PROGRESS: 0
    [6]DOWNSTREAM_PORT_STATUS_CHANGED: 0
    [7]LINK_STATUS_UPDATED: 1
00205h SINK_STATUS
    [0]RECEIVE_PORT_0_STATUS: 0,Sink device is out of synchronization
    [1]RECEIVE_PORT_1_STATUS: 0,Sink device is out of synchronization
    [2]STREAM_REGENERATION_STATUS: 1,Stream is being regenerated
00206h ADJUST_REQUEST_LANE0_1
    [1:0]VOLTAGE_SWING_LANE0: 0,Level 0
    [3:2]PRE-EMPHASIS_LANE0: 1,Level 1
    [5:4]VOLTAGE_SWING_LANE1: 0,Level 0
    [7:6]PRE-EMPHASIS_LANE1: 1,Level 1
00207h ADJUST_REQUEST_LANE2_3
    [1:0]VOLTAGE_SWING_LANE0: 0,Level 0
    [3:2]PRE-EMPHASIS_LANE0: 1,Level 1
    [5:4]VOLTAGE_SWING_LANE1: 0,Level 0
    [7:6]PRE-EMPHASIS_LANE1: 1,Level 1

結束Link Training

➕Native Write(8) Addr:0x00102 Length:1 Data:00

00102h TRAINING_PATTERN_SET

[3:0]TRAINING_PATTERN_SELECT: 0,Training not in progress (or disabled)

[4]RECOVERED_CLOCK_OUT_EN: 0,Recovered clock output from a test pad of DPRX is not enabled

[5]SCRAMBLING_DISABLE: 0,DPTX scrambles data symbols before transmission

[7:6]SYMBOL_ERROR_COUNT_SEL: 0,Count Disparity and Illegal Symbol errors

➕Native Write(8) Addr:0x0010A Length:1 Data:01

0010Ah eDP_CONFIGURATION_SET

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